Memory test algorithms are written to uncover faults with storage cells and the access to these storage cells arising from improper design, lack of design margins or processing deficiencies. Generally, these algorithms are written to be extensive and exhaustive to ensure that no bit defects, either hard defects or intermittent failures find their way into the field.
Understanding memory fail modes is crucial to providing accurate corrective actions to wafer fabrications for sustained yield improvements. Current test algorithms are aimed at detecting bits that do not meet a certain performance criteria. In one failure mode (hard fail), bits may be stuck at a certain data state at all voltages, or in another failure mode (soft fail) the bits may be unable to be read from or written to at certain voltages. When these soft fails occur, it is usually at the extreme voltage corners of a device voltage range, but failures within a smaller voltage range, or what is known in the industry as “shmoo hole fails” are also not unusual.
These defective bits are identified as bad during test and repaired using redundant bits. When it is not possible to repair all the bad bits, the chip is marked as defective and rejected during bin sorting. No attempt is made to identify the failure mode. Reject units are then taken off line for further electrical analysis and later, perhaps physical failure analysis. During off-line analysis, more extensive voltage, temperature and timing characterization is performed to determine the conditions at which the bad bits begin to pass. More elaborate testing on the target fail bits may be done to determine if the failure is a write, a read or a disturb failure. This determination is usually performed by reading or writing at a known passing voltage and then writing and reading at the failing voltages. However, it is much more difficult to tell if a bit is failing due to a disturb failure or a read failure as cells always go through a disturb phase before they are read.
A write fail would suggest that the pass gate or access transistor is weak relative to the load transistor and the drive transistor. Hence, by increasing the drive current for access transistors through bit re-design, transistor engineering, or boosting the word line voltage during write cycles, write fails could be minimized once this failure mode is identified.
A read fail suggests that there may be insufficient voltage differential across the sense amplifiers when the amplifiers are enabled. For fast access times, sense amplifiers are turned on as soon as it is thought that there is enough voltage developed across the bit line and its complement, based on simulations. If the access transistors, and/or driver devices are weaker than expected, the bit line voltage differentials will not be sufficient to overcome imbalances in the sense amplifiers and an incorrect data state is output. This incorrect state may or may not be written back into the bit.
As many bits are connected to a single word line, all bits along the accessed word line will be enabled (bits connected to their respective bit lines). Not all bit lines, however, are connected to the sense amplifiers. Only those bits that are to be read will have their bit lines connected to the sense amplifiers via local and global multiplexers. In other words, not all cells along the accessed word line are read. Despite not being read, when cells are imbalanced, the act of connecting them to bit lines that are pre-charged to the supply voltage (e.g., Vcc) can result in cell upsets. One reason for an upset is a low Vt on the driver of the side of the bit wherein a “1” data state is stored. Another reason for an upset may be that the load transistors are weak. Hence, a strong N channel and a weak P channel condition within the memory device would cause disturb fails.
In addition, data retention tests are also being performed with more frequency lately as memory cells are required to retain data in a sleep mode or what is commonly referred to as “data retention” mode. In this mode, storage cells have reduced voltages applied across them to minimize leakage currents during the standby condition. Accordingly, there is a growing need for testing data retention failures that may arise as a result of such leakage conditions in the manufacturing of semiconductor memory devices.
It is clear that depending on the failure type, different corrective actions will be chosen to improve electrical bit yield and hence swift and accurate real-time analysis is of high importance to providing directions for future production lot starts and design modifications.
Semiconductor memories can, for example, be characterized as volatile random access memories (RAMs) or nonvolatile read only memories (ROMs), where RAMs can either be static (SRAM) or dynamic (DRAM) differing mainly in the manner by which they store a state of a bit. In SRAM, for example, each memory cell includes transistor-based circuitry that implements a bistable latch, which relies on transistor gain and positive (e.g., reinforcing) feedback so that it can only assume one of two possible states, namely on (state 1) or off (state 2). The latch can only be programmed or induced to change from one state to the other through the application of a voltage or other external stimuli. This arrangement is desirable for a memory cell since a state written to the cell will be retained until the cell is reprogrammed.
DRAMs on the other hand implement a capacitor that is either charged or discharged to store the on (state 1) or off (state 2) state of a cell. Capacitors discharge over time, however, and DRAMs must therefore be periodically ‘refreshed’. Also, a bistable latch can generally be switched between states much faster than the amount of time it takes to charge or discharge a capacitor. Accordingly, SRAMs are a desirable type of memory for certain types of applications.
SRAM is typically arranged as a matrix of memory cells fabricated in an integrated circuit chip, and address decoding in the chip allows access to each cell for read/write functions. SRAM memory cells use active feedback from cross-coupled inverters in the form of a latch to store or “latch” a bit of information. These SRAM memory cells are often arranged in rows so that blocks of data such as words or bytes can be written or read simultaneously. Standard SRAM memory cells have many variations. The basic CMOS SRAM cell generally includes two n-type (nMOS) pull-down or drive transistors and two p-type (pMOS) load transistors in a cross-coupled inverter configuration, with two additional nMOS select transistors added to make up a six-transistor cell (a 6T cell).
Accordingly, there is a need for a memory testing technique to quickly differentiate between various soft bit failure modes particularly in an SRAM device in a production testing environment.